Variability and energy awareness: a microarchitecture-level perspective
Variability and energy awareness: a microarchitecture-level perspective
复制标题
可变性和能源意识：微架构层面的视角
DOI：
10.1145/1065579.1065588
复制
发表时间：
2005
期刊：
影响因子：
--
通讯作者：
Emil Talpes
中科院分区：
文献类型：
--
作者：
Diana Marculescu;Emil Talpes
本文提出了微体系结构级模型内管芯（WID）的过程和系统参数的变化，可以包括在高性能处理器的设计。由于在微体系结构级别上做出的决定一方面对性能和功耗影响最大，另一方面对全局可变性影响最大，因此需要模型和相关指标来进行联合表征和分析。为了评估这些变化如何影响或受微架构决策的影响，我们提出了一个联合的性能，功率和可变性指标，能够区分各种设计选择。作为一个设计驱动程序的建模方法，我们认为一个集群的高性能处理器的实现，沿着与其全球异步，本地同步（GALS）的对口。结果表明，当比较基线，同步及其GALS对应物时，微架构驱动的工艺可变性的影响转化为GALS情况下2-10%的本地时钟快，而当考虑到片上温度变化的影响时，本地时钟可以快8-18%。此外，如果采用电压缩放（DVS），则具有DVS的GALS架构在采用能量、性能和可变性的联合质量度量方面好26%。
This paper proposes microarchitecture-level models for within die (WID) process and system parameter variability that can be included in the design of high-performance processors. Since decisions taken at microarchitecture level have the largest impact on both performance and power, on one hand, and global variability effect, on the other hand, models and associated metrics are needed for their joint characterization and analysis. To assess how these variations affect or are affected by microarchitecture decisions, we propose a joint performance, power and variability metric that is able to distinguish among various design choices. As a design-driver for the modeling methodology, we consider a clustered high-performance processor implementation, along with its globally asynchronous, locally synchronous (GALS) counterpart. Results show that, when comparing the baseline, synchronous and its GALS counterpart, microarchitecture-driven impact of process variability translates into 2-10% faster local clocks for the GALS case, while when taking into account the effect of on-chip temperature variability, local clocks can be 8-18% faster. If, in addition, voltage scaling (DVS) is employed, the GALS architecture with DVS is 26% better in terms of the joint quality metric employing energy, performance, and variability.