CMOS compatible many-core noc architectures with multi-channel millimeter-wave wireless links

CMOS compatible many-core noc architectures with multi-channel millimeter-wave wireless links
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具有多通道毫米波无线链路的 CMOS 兼容多核 noc 架构

DOI:
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发表时间:
2012
期刊:
ACM Great Lakes Symposium on VLSI
影响因子:
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通讯作者:
B. Belzer
B. Belzer
中科院分区:
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文献类型:
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作者:
Sujay Deb;Kevin Chang;Miralem Cosic;A. Ganguly;P. Pande;D. Heo;B. Belzer

文献摘要

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传统的基于片上网络(NoC)范式的众核设计由于其固有的多跳通信而随着系统规模的扩大而遭受高延迟和功耗。通过在相距甚远的核之间引入长距离、低功耗和高带宽的单跳无线链路,可以显著增强NoC性能。本文提出了一种分层小世界片上网络的设计方法和性能评估与CMOS兼容的片上毫米波(mm)无线远程通信链路。所提出的无线片上网络提供了显着更高的带宽和更低的能耗相比,其传统的非分层有线对应的存在下,均匀和非均匀的流量模式。通过高效的数据路由和无线集线器的最佳放置来实现性能改进。多个无线快捷方式同时运行为众核通信基础设施的设计提供了一种节能解决方案。
Traditional many-core designs based on the Network-on-Chip (NoC) paradigm suffer from high latency and power dissipation as the system size scales up due to their inherent multi-hop communication. NoC performance can be significantly enhanced by introducing long-range, low power, and high-bandwidth single-hop wireless links between far apart cores. This paper presents a design methodology and performance evaluation for a hierarchical small-world NoC with CMOS compatible on-chip millimeter (mm)-wave wireless long-range communication links. The proposed wireless NoC offers significantly higher bandwidth and lower energy dissipation compared to its conventional non-hierarchical wired counterpart in presence of both uniform and non-uniform traffic patterns. The performance improvement is achieved through efficient data routing and optimum placement of wireless hubs. Multiple wireless shortcuts operating simultaneously provide an energy efficient solution for design of many-core communication infrastructures.