A self-test methodology for IP cores in bus-based programmable SoCs
A self-test methodology for IP cores in bus-based programmable SoCs
复制标题
基于总线的可编程 SoC 中 IP 核的自测试方法
DOI：
10.1109/vts.2001.923439
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发表时间：
2001
期刊：
影响因子：
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通讯作者：
K. Cheng
中科院分区：
文献类型：
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作者：
Jing;Madhu K. Iyer;K. Cheng
我们提出了一种新的测试方法，用于测试具有嵌入式处理器内核的soc中的IP内核。测试程序在处理器内核上运行，生成测试模式并将其传递到SoC中的目标IP内核，并分析测试响应。这为可以应用于IP核的模式类型提供了极大的灵活性，而不会产生显著的硬件开销。我们使用基于总线的SoC仿真模型来验证我们的测试方法。测试方法包括添加测试包装器，该包装器可以针对特定的测试需求进行配置。该方法支持实现全扫描的IP核的延迟故障和卡在测试的高速测试。
We present a novel test methodology for testing IP cores in SoCs with embedded processor cores. A test program is run on the processor core that generates and delivers test patterns to the target IP cores in the SoC and analyzes the test responses. This provides tremendous flexibility in the type of patterns that can be applied to the IP cores without incurring significant hardware overhead. We use a bus based SoC simulation model to validate our test methodology. The test methodology involves addition of a test wrapper that can be configured for specific test needs. The methodology supports at-speed testing for delay faults and stuck-at testing of IP cores implementing full-scan.