Exploiting Partial Runtime Reconfiguration for High-Performance Reconfigurable Computing
Exploiting Partial Runtime Reconfiguration for High-Performance Reconfigurable Computing
复制标题
利用部分运行时重配置实现高性能可重配置计算
DOI:
10.1145/1462586.1462590
复制
发表时间:
2009
期刊:
影响因子:
--
通讯作者:
T. El
中科院分区:
文献类型:
--
作者:
E. El;I. González;T. El
Runtime Reconfiguration (RTR) has been traditionally utilized as a means for exploiting the flexibility of High-Performance Reconfigurable Computers (HPRCs). However, the RTR feature comes with the cost of high configuration overhead which might negatively impact the overall performance. Currently, modern FPGAs have more advanced mechanisms for reducing the configuration overheads, particularly Partial Runtime Reconfiguration (PRTR). It has been perceived that PRTR on HPRC systems can be the trend for improving the performance. In this work, we will investigate the potential of PRTR on HPRC by formally analyzing the execution model and experimentally verifying our analytical findings by enabling PRTR for the first time, to the best of our knowledge, on one of the current HPRC systems, Cray XD1. Our approach is general and can be applied to any of the available HPRC systems. The paper will conclude with recommendations and conditions, based on our conceptual and experimental work, for the optimal utilization of PRTR as well as possible future usage in HPRC.