Efficient Memristor-Based Architecture for Intrusion Detection and High-Speed Packet Classification
Efficient Memristor-Based Architecture for Intrusion Detection and High-Speed Packet Classification
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DOI：
10.1145/3264819
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发表时间：
2018-12-01
影响因子：
2.2
通讯作者：
Taha, Tarek M.
中科院分区：
文献类型：
--
作者：
Bontupalli, Venkataramesh;Yakopcic, Chris;Taha, Tarek M.
深度包检测（DPI）是防止入侵检测的关键组件。这需要详细分析每个网络数据包的报头和主体。虽然这通常在大多数联网系统中的专用高功率服务器上进行，但是如果在未受保护的网络上使用，则移动的系统可能潜在地容易受到攻击。在这种情况下，在移动的系统上具有DPI硬件将是非常有益的。不幸的是，DPI硬件通常是面积和功耗，使其难以在移动的systems.We开发了一个忆阻器交叉开关为基础的方法，灵感来自忆阻器交叉开关神经形态电路，低功耗，低面积，高吞吐量的DPI系统，检查一个数据包的头部和身体。两个关键类型的电路：静态模式匹配和正则表达式电路。该系统能够减少执行时间和功耗，由于其高密度的网格和大量的并行。独立的搜索进行使用低功耗meinristor交叉阵列产生的吞吐量为160Gbps的分类精度没有损失。
Deep packet inspection (DPI) is a critical component to prevent intrusion detection. This requires a detailed analysis of each network packet header and body. Although this is often done on dedicated high-power servers in most networked systems, mobile systems could potentially be vulnerable to attack if utilized on an unprotected network. In this case, having DPI hardware on the mobile system would be highly beneficial. Unfortunately, DPI hardware is generally area and power consuming, making its implementation difficult in mobile systems.We developed a memristor crossbar-based approach, inspired by memristor crossbar neuromorphic circuits, for a low-power, low-area, and high-throughput DPI system that examines both the header and body of a packet. Two key types of circuits are presented: static pattern matching and regular expression circuits. This system is able to reduce execution time and power consumption due to its high-density grid and massive parallelism. Independent searches are performed using low-power meinristor crossbar arrays giving rise to a throughput of 160Gbps with no loss in the classification accuracy.