Integrated Circuit Modeling for Noise Susceptibility Prediction in Communication Networks
Integrated Circuit Modeling for Noise Susceptibility Prediction in Communication Networks
复制标题
用于通信网络中噪声敏感性预测的集成电路建模
DOI：
10.1109/temc.2015.2406664
复制
发表时间：
2015
影响因子：
2.1
通讯作者：
R. Perraud
中科院分区：
文献类型：
--
作者：
M. Fontana;F. Canavero;R. Perraud
本文讨论了通信网络混合信号抗扰度仿真的集成电路 (IC) 建模过程。该过程基于灰盒方法，使用物理电路对 (IC) 端口进行建模，并使用行为块对内部链路进行建模。这些参数是根据时域和频域测量来估计的，从而可以准确有效地再现非线性器件的开关行为。通过将所提出的技术应用于控制器局域网（CAN）收发器（涉及数据通信链路上的直接功率注入（DPI）抗扰度测试）来验证建模过程的有效性。所获得的模型已成功在 VHDL 模拟混合信号 (AMS) 求解器中实现，以预测组件级的功能信号和射频噪声抗扰度。
This paper addresses an integrated circuit (IC) modeling procedure for mixed-signal immunity simulations of communication networks. The procedure is based on a gray-box approach, modeling (IC) ports with a physical circuit and the internal links with a behavioral block. The parameters are estimated from time and frequency domain measurements, allowing accurate and efficient reproduction of nonlinear device switching behaviors. The effectiveness of the modeling process is verified by applying the proposed technique to a controller area network (CAN) transceiver, involved in a direct power injection (DPI) immunity test on a data communication link. The obtained model is successfully implemented in a VHDL-analog mixed-signal (AMS) solver to predict both the functional signals and the RF noise immunity at component level.