Analog and digital circuit design in 65 nm CMOS: end of the road?
Analog and digital circuit design in 65 nm CMOS: end of the road?
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DOI：
10.1109/date.2005.64
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发表时间：
2005-03
期刊：
影响因子：
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通讯作者：
G. Gielen;W. Dehaene;P. Christie;D. Draxelmayr;E. Janssens;K. Maex;T. Vucurevich
中科院分区：
文献类型：
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作者：
G. Gielen;W. Dehaene;P. Christie;D. Draxelmayr;E. Janssens;K. Maex;T. Vucurevich
这个介绍性的嵌入式教程给出了在纳米级CMOS技术设计集成电子系统时手头的设计问题的概述。首先，一些影响电路设计的一般问题得到解决，如增加的泄漏和可变性与缩放技术。接下来，讨论这对数字电路设计和嵌入式存储器的影响。最后，提出了嵌入式模拟电路存在的问题，如降低电源电压、设计效率低和信号完整性问题。解决这些问题将决定设计道路是否在CMOS技术标志“65纳米”结束。
This introductory embedded tutorial gives an overview of the design problems at hand when designing integrated electronic systems in nanometer-scale CMOS technologies. First, some general problems that affect circuit design are addressed, such as the increased leakage and variability with scaling technologies. Next, the impact of this on digital circuit design and embedded memories is discussed. Finally, problems bothering embedded analog circuits are presented, such as reducing supply voltages, poor design productivity and signal integrity troubles. Addressing these problems will determine whether the design road ends at CMOS technology marker "65 nm " or not.