Electrical model of the floating gate defect in CMOS ICs: implications on IDDQ testing
Electrical model of the floating gate defect in CMOS ICs: implications on IDDQ testing
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CMOS IC 中浮栅缺陷的电气模型：对 IDDQ 测试的影响
DOI：
10.1109/43.265677
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发表时间：
1994
期刊：
影响因子：
--
通讯作者：
J. Figueras
中科院分区：
文献类型：
--
作者：
V. Champac;A. Rubio;J. Figueras
本文研究了MOS晶体管在多晶硅栅通路中存在开路（浮置晶体管栅缺陷）时的行为及其对静态电源电流I/sub DDQ/的影响。在完全互补的CMOS电路中，探讨了通过电流测试来检测这种缺陷的可能性。使用浮栅中的耦合电容和晶体管栅极中的电荷对具有浮栅的晶体管的行为进行建模。的多晶硅体和金属多晶硅电容被发现是两个重要的参数，在确定受影响的晶体管的导电程度。浮栅感应电压和静态电流的解析表达式估计。该模型与SPICE 2模拟进行了比较。简单的解析表达式、仿真和对缺陷电路进行的实验测量之间观察到良好的一致性。此外，它示出的浮栅晶体管可以被建模为一个弱导电的粘在晶体管或作为一个粘在打开的晶体管取决于表征缺陷的参数的值。>
The behavior of an MOS transistor with an open in the polygate path (floating transistor gate defect) is investigated and its effect on the quiescent power supply current I/sub DDQ/ is studied. The possible detection of this defect by current testing is explored in fully complementary CMOS circuits. The behavior of a transistor with its floating gate is modeled using the coupling capacitances in the floating gate and the charge in the transistor gate. The poly-bulk and metal-poly capacitances are found to be two significant parameters in determining the degree of conduction on the affected transistor. The induced voltage in the floating gate and the quiescent current are estimated by analytical expressions. The model is compared with SPICE 2 simulations. Good agreement is observed between the simple analytical expressions, simulations and experimental measures performed on defective circuits. In addition, it is shown that the floating gate transistor can be modeled as a weakly conductive stuck-on transistor or as a stuck-open transistor depending on the values of the parameters characterizing the defect. >