Grain boundary electrical barriers in positive temperature coefficient thermistors
Grain boundary electrical barriers in positive temperature coefficient thermistors
复制标题
正温度系数热敏电阻中的晶界电势垒
DOI：
10.1063/1.371140
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发表时间：
1999
影响因子：
3.2
通讯作者：
T. Sakuma
中科院分区：
文献类型：
--
作者：
K. Hayashi;Takahisa Yamamoto;Y. Ikuhara;T. Sakuma
电阻-温度，电流-电压和电容-电压特性已被测量在掺杂钛酸钡双晶体。器件模拟分析表明，势垒与半导体-绝缘体-半导体结构可以一致地解释所观察到的特性，而不是双肖特基势垒。在电流-电压特性中的亚欧姆行为的缺乏和过量的低频电容在零偏置是由空间分布的陷阱在绝缘层。
Resistance–temperature, current–voltage, and capacitance–voltage characteristics have been measured in niobium-doped barium titanate bicrystals. The analysis by device simulation reveals that potential barrier with a semiconductor–insulator–semiconductor structure can consistently interpret the observed characteristics rather than the double Schottky barrier. Absence of sub-ohmic behavior in the current–voltage characteristics and excess low-frequency capacitance at zero bias are caused by the spatially distributed traps at the insulating layer.