The design of scalar AES Instruction Set Extensions for RISC-V
The design of scalar AES Instruction Set Extensions for RISC-V
复制标题
RISC-V标量AES指令集扩展设计
DOI：
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发表时间：
2020
期刊：
影响因子：
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通讯作者：
Claire Wolf
中科院分区：
文献类型：
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作者：
Ben Marshall;G. R. Newell;D. Page;Markku;Claire Wolf
安全、高效地执行AES是大多数计算平台的基本要求。为此，通常会包含专用指令集扩展（ISE）。RISC-V是一个（相对）新的伊萨，缺乏这样一个标准化的伊势。我们调查国家的最先进的工业和学术的AES ISE，实现和评估五个不同的ISE，其中之一是新颖的。我们建议为32位和64位基础架构使用单独的ISE，与基于使用T表的纯软件实现相比，AES-128块加密的测量性能提高了4倍和10倍，硬件成本分别为1.1K和8.2K门。我们还探索如何利用RISC-V的拟议标准位操作扩展来高效实现AES-GCM。我们的工作支持正在进行的RISC-V加密扩展标准化过程。
Secure, efficient execution of AES is an essential requirement on most computing platforms. Dedicated Instruction Set Extensions (ISEs) are often included for this purpose. RISC-V is a (relatively) new ISA that lacks such a standardised ISE. We survey the state-of-the-art industrial and academic ISEs for AES, implement and evaluate five different ISEs, one of which is novel. We recommend separate ISEs for 32 and 64-bit base architectures, with measured performance improvements for an AES-128 block encryption of 4× and 10× with a hardware cost of 1.1K and 8.2K gates respectively, when compared to a software-only implementation based on use of T-tables. We also explore how the proposed standard bit-manipulation extension to RISC-V can be harnessed for efficient implementation of AES-GCM. Our work supports the ongoing RISC-V cryptography extension standardisation process.