An area-efficient 4/8/16/32-point inverse DCT architecture for UHDTV HEVC decoder
An area-efficient 4/8/16/32-point inverse DCT architecture for UHDTV HEVC decoder
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DOI：
10.1109/vcip.2014.7051538
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发表时间：
2014-12
期刊：
影响因子：
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通讯作者：
Heming Sun;Dajiang Zhou;Jiayi Zhu;S. Kimura;S. Goto
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文献类型：
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作者：
Heming Sun;Dajiang Zhou;Jiayi Zhu;S. Kimura;S. Goto
提出了一种新的用于HEVC反离散余弦变换（TDCT）的VLSI结构。与现有技术相比，这项工作通过以下方式降低了硬件成本：通过共享蝶形结构输入的重排序并行输入串行输出（RPISO）方案减少了1-D idct的计算逻辑；以及使用循环存储器组织减少转置缓冲区的面积，该循环存储器组织实现所述sram的100% I/O利用率。在实现统一的4/8/16/32点IDCT时，所提出的方案分别降低了35%和62%的逻辑和存储成本。IDCT实现可以支持4K×2K 60fps视频的实时解码，2d IDCT的总硬件成本为357,250um2，转置存储器的总硬件成本为80,988um2。
This paper presents a new VLSI architecture for HEVC inverse discrete cosine transform (TDCT). Compared to prior arts, this work reduces hardware cost by: reducing computational logic of 1-D IDCTs with a reordered parallel-in serial-out (RPISO) scheme that shares the inputs of the butterfly structure; and reducing the area of the transpose buffer with a cyclic memory organization that achieves 100% I/O utilization of the SRAMs. In the implementation of a unified 4/8/16/32-point IDCT, the proposed schemes demonstrate 35% and 62% reduction of logic and memory costs, respectively. The IDCT implementation can support real-time decoding of 4K×2K 60fps video with a total hardware cost of 357,250um2 on 2-D IDCT and 80,988um2 on transpose memory in 90nm process.