A 12.8-Gb/s/link Tri-Modal Single-Ended Memory Interface
A 12.8-Gb/s/link Tri-Modal Single-Ended Memory Interface
复制标题
12.8 Gb/s/链路三模式单端内存接口
DOI：
10.1109/jssc.2012.2185369
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发表时间：
2012
影响因子：
5.4
通讯作者：
Xingchao Yuan
中科院分区：
文献类型：
--
作者：
A. Amirkhany;Jason Wei;N. Mishra;Jie Shen;W. Beyene;Catherine Chen;T. Chin;D. Dressler;Charlie Huang;V. Gadde;M. Hekmat;K. Kaviani;H. Lan;P. Le;Mahabaleshwara;C. Madden;S. Mukherjee;L. Raghavan;Keisuke Saito;D. Secker;A. Sendhil;R. Schmitt;H. Fazeel;G. Srinivas;Ting Wu;C. Tran;A. Vaidyanath;K. Vyas;Ling Yang;Manish Jain;Ken Chang;Xingchao Yuan
本文提出了一种三模式非对称内存控制器接口，可在 3" 带状线 FR4 走线上实现 12.8 Gbps 单端 (SE) 信号传输。该控制器可配置为分别以 6.4 和 1.6 Gbps 与市售 GDDR5 和 DDR3 内存进行通信，而无需更改封装。该接口配备了紧凑型电压模式驱动器，在写入方向具有 1 抽头预加重功能和线性均衡器(LEQ) 和 1 抽头判决反馈均衡器 (DFE)，在 READ 方向，以补偿通道符号间干扰 (ISI)。 接收器前端包含一个电源噪声跟踪方案，以减轻参考电压 (VREF) 噪声。 × 16 三模接口采用 40 nm CMOS 工艺实现，在 12.8 Gbps 时每条数据链路的能效优于 5.0 mW/Gbps。
This paper presents a tri-modal asymmetric memory controller interface that achieves 12.8-Gbps single-ended (SE) signaling over 3" stripline FR4 traces. The controller can be configured to communicate with commercially available GDDR5 and DDR3 memories at 6.4 and 1.6 Gbps, respectively, with no package change. The interface is equipped with a compact voltage-mode driver with 1-tap pre-emphasis, in the WRITE direction, and a linear equalizer (LEQ) and 1-tap decision feedback equalizer (DFE), in the READ direction, to compensate for channel inter-symbol interference (ISI). The receiver front-end contains a supply noise tracking scheme to mitigate reference voltage (VREF) noise. A tri-VCO PLL and an efficient global clock distribution scheme support a wide range of operating frequencies at low power consumption. Finally, the interface also incorporates two overhead links per byte for data-bus encoding (DBE) experiments to mitigate simultaneous switching noise (SSN). Implemented in a 40-nm CMOS process, the × 16 tri-modal interface achieves an energy efficiency of better than 5.0 mW/Gbps per data link at 12.8 Gbps.