Super-junction LDMOST on a silicon-on-sapphire substrate
Super-junction LDMOST on a silicon-on-sapphire substrate
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DOI：
10.1109/ted.2003.813460
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发表时间：
2003-07
影响因子：
3.1
通讯作者：
S. Nassif-Khalil;C. Salama
中科院分区：
文献类型：
--
作者：
S. Nassif-Khalil;C. Salama
针对功率集成电路提出了一种蓝宝石上硅超结横向双扩散MOST（SJ-LDMOST）技术，并进行了实现和表征。所提出的结构消除了横向SJ器件中的“衬底辅助耗尽”效应，从而实现了n和p SJ柱之间的电荷补偿以及在关断状态下漂移区中的均匀电场分布。三维（3-D）模拟的设备，使用现实的纵横比的SJ柱，表明一个显着减少特定的导通电阻，对于一个给定的击穿电压可以实现相比，传统的减少表面场（RESURF）设备。使用七掩模CMOS兼容工艺实现了实验器件。具有66 /spl mu/m的漂移区长度和1.2 /spl mu/m/0.7 /spl mu/m（宽度/高度）的柱纵横比的所制造的SJ-LDMOS表现出0.82 /spl Ω/cm/sup 2/的比导通电阻和对应于柱中小于8.5%的电荷不平衡的在500和600 V之间的范围内的击穿电压（BV）。
A super-junction lateral double diffused MOST (SJ-LDMOST) in silicon-on-sapphire technology, targeting power integrated circuits (PICs), is proposed, implemented and characterized. The proposed structure eliminates "substrate-assisted-depletion" effects in lateral SJ devices thus achieving charge compensation between the n and p SJ-pillars as well as a uniform electric field distribution in the drift region in the off-state. Three-dimensional (3-D) simulations of the device, using realistic aspect ratios for the SJ-pillars, indicate that a significant reduction in specific on-resistance for a given breakdown voltage can be achieved as compared to conventional reduced surface field (RESURF) devices. Experimental devices were implemented using a seven mask CMOS compatible process. Fabricated SJ-LDMOSTs with a drift region length of 66 /spl mu/m and a pillar aspect ratio of 1.2 /spl mu/m/0.7 /spl mu/m (width/height) exhibit a specific on-resistance of 0.82 /spl Omega/.cm/sup 2/ and a breakdown voltage (BV) ranging between 500 and 600 V corresponding to less than 8.5% charge imbalance in the pillars.