A 32 × 32 BIT multiplier using multiple-valued MOS current-mode circuits
A 32 × 32 BIT multiplier using multiple-valued MOS current-mode circuits
复制标题
使用多值 MOS 电流模式电路的 32 × 32 BIT 乘法器
DOI：
10.1109/4.268
复制
发表时间：
1987
期刊：
影响因子：
--
通讯作者：
Haruyasu Yamada
中科院分区：
文献类型：
--
作者：
S. Kawahito;M. Kameyama;T. Higuchi;Haruyasu Yamada
在传统的阵列乘法器中，乘法速度受到进位传播的限制。另一方面，在诸如华莱士树乘法器的高速乘法器中难以实现紧凑乘法器，因为其布局复杂并且需要大面积用于互连。在这种情况下，在传统数字系统中使用多值逻辑具有潜在的优势，其中最重要的优势之一是减少互连[1]。然而，很少有类型的芯片使用多值逻辑已经制造的实际应用[2]。本文提出了一种基于基4符号数字（SD）数系统的高速紧凑乘法器和一种使用多值MOS电流模式电路的全新实现[3]。
In the conventional array multiplier, the multiplication speed is restricted by the carry propagation. On the other hand, it is difficult to realize a compact multiplier in the high-speed multiplier such as the Wallace tree multiplier, because its layout is complicated and a large area is required for the interconnections. In such situations, the use of multiple-valued logic in conventional digital systems has potential advantages of which one of the most important is the reduction in interconnections [1]. However very few types of chips using multiple-valued logic have been fabricated for practical applications[2]. This paper presents a high-speed compact multiplier based on the radix-4 signed-digit (SD) number system and a completely new implementation using multiple-valued MOS current-mode circuits[3].