A Layout-Aware Pattern Grading Procedure for Critical Paths Considering Power Supply Noise and Crosstalk
A Layout-Aware Pattern Grading Procedure for Critical Paths Considering Power Supply Noise and Crosstalk
复制标题
考虑电源噪声和串扰的关键路径的布局感知模式分级程序
DOI：
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发表时间：
2012
期刊：
影响因子：
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通讯作者：
P. Girard
中科院分区：
文献类型：
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作者：
Junxia Ma;M. Tehranipoor;P. Girard
在数字集成电路中，电源噪声和串扰是两种主要的模式相关噪声源，对信号的完整性有负面影响。这些噪声源在低于65nm的技术中发挥更大的作用，可能导致设计中的时序故障和可靠性问题；因此，在测试模式生成和验证期间必须仔细考虑。在本文中，我们提出了一种新的方法来评估路径延迟故障测试模式在目标关键路径上造成过多延迟的能力。它利用激活的干扰门和网络信息对噪声进行量化，并给出模式质量值(Q)。该方法为设计工程师提供了一种快速的方法来评估静态时序分析（STA）和硅中的关键路径，以改进时序裕度策略。通过评估失败的测试模式，所提出的方法可用于在故障分析期间帮助识别根本原因。仿真结果验证了该方法的有效性和有效性。
Power supply noise and crosstalk are the two major noise sources that are pattern dependent and negatively impact signal integrity in digital integrated circuits. These noise sources play a greater role in sub-65nm technologies and may cause timing failures and reliability problems in a design; thus must be carefully taken into consideration during test pattern generation and validation. In this paper, we propose a novel method to evaluate path-delay fault test patterns in terms of their ability to cause excess delay on targeted critical paths. It quantifies the noises with a pattern quality value (Q) using the activated aggressor gates and nets information. The proposed method offers design engineers a quick approach to evaluate the critical paths in static timing analysis (STA) and silicon to improve timing margin strategies. By evaluating the failed test pattern, the proposed method can be used to help identify the root cause during failure analysis. Simulation results demonstrate the efficiency and effectiveness of the pattern grading procedure.