Time dependence of bias-stress-induced SiC MOSFET threshold-voltage instability measurements
Time dependence of bias-stress-induced SiC MOSFET threshold-voltage instability measurements
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DOI：
10.1109/ted.2008.926672
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发表时间：
2008-08-01
影响因子：
3.1
通讯作者：
Goldsman, Neil
中科院分区：
文献类型：
--
作者：
Lelis, Aivars J.;Habersat, Daniel;Goldsman, Neil
我们已经观察到显着的不稳定性的阈值电压的4 H-SiC金属氧化物半导体场效应晶体管由于栅极偏置应力。这种效应具有很强的测量时间依赖性。例如，发现用于测量I-V特性并提取阈值电压的20 ps长的栅极斜坡导致的VT不稳定性比用I-s长的栅极斜坡测量的VT不稳定性大三到四倍。VT的不稳定性是三倍更大的设备，没有收到NO后氧化退火相比，那些。这种不稳定性的影响是一致的电子直接隧道进出近界面的氧化物陷阱，这在辐照的硅MOS是由于边界陷阱。
We have observed significant instability in the threshold voltage of 4H-SiC metal-oxide-semiconductor field-effect transistors due to gate-bias stressing. This effect has a strong measurement time dependence. For example, a 20-ps-long gate ramp used to measure the I-V characteristic and extract a threshold voltage was found to result in a VT instability three to four times greater than that measured with a I-s-long gate ramp. The VT instability was three times greater in devices that did not receive a NO postoxidation anneal compared with those that did. This instability effect is consistent with electrons directly tunneling in and out of near-interfacial oxide traps, which in irradiated Si MOS was attributed to border traps.