COMPACTEST-II: a method to generate compact two-pattern test sets for combinational logic circuits
COMPACTEST-II: a method to generate compact two-pattern test sets for combinational logic circuits
复制标题
COMPACTEST-II：一种为组合逻辑电路生成紧凑的双模式测试集的方法
DOI：
--
复制
发表时间：
1992
期刊：
影响因子：
--
通讯作者：
S. Reddy
中科院分区：
文献类型：
--
作者：
L. Reddy;I. Pomeranz;S. Reddy
研究了组合逻辑电路中单跃迁和CMOS卡开路故障的小(紧)测试集生成问题。此外，为了生成覆盖广泛物理缺陷的测试集，应该推导出用于检测不同模型的故障的测试集。具体地说，通过同时考虑CMOS卡开型故障模型和单过渡故障模型，解决了生成小而全面的测试集的问题。提出了一种适用于双模试验的动测压实技术。该技术利用针对固定故障开发的测试紧凑策略，并执行动态测试向量重叠来派生小测试集。给出了ISCAS-85组合电路和ISCAS-89时序电路全扫描版本的实验结果，以说明所提出的测试紧凑技术的有效性。
The problem of generating small (compact) test sets for single transition and CMOS stuck-open faults in combinational logic circuits is considered. In addition, it is proposed that to generate test sets that cover a wide range of physical defects, a test set to detect faults of different models should be derived. Specifically, the problem of generating small and comprehensive test sets is addressed by considering the CMOS stuck-open and the single transition fault models together. A dynamic test compaction technique for two-pattern tests is proposed. The technique exploits the test compaction strategies developed for stuck-at faults, and performs dynamic test vector overlap to derive small test sets. Experimental results for ISCAS-85 combinational circuits and fully scanned versions of ISCAS-89 sequential circuits are presented to illustrate the efficacy of the proposed test compaction technique.<<ETX>>