A VLSI array of low-power spiking neurons and bistable synapses with spike-timing dependent plasticity
A VLSI array of low-power spiking neurons and bistable synapses with spike-timing dependent plasticity
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DOI：
10.1109/tnn.2005.860850
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发表时间：
2006-01-01
影响因子：
--
通讯作者：
Douglas, R
中科院分区：
文献类型：
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作者：
Indiveri, G;Chicca, E;Douglas, R
我们提出了一种混合模式模拟/数字VLSI器件，包括一系列泄漏集成和发射（I&F）神经元，具有峰值时间依赖可塑性的自适应突触，以及基于异步事件的通信基础设施，该基础设施允许用户（重新）配置具有任意拓扑的峰值神经元网络。硅神经元用于在芯片外传输尖峰（事件）和硅突触用于从外部接收尖峰的异步通信协议基于“地址-事件表示”（AER）。我们描述了设计用于实现硅神经元和突触的模拟电路，并提供了实验数据，显示了神经元响应特性和突触特征，以响应AER输入尖峰串。我们的研究结果表明，这些电路可以用于大规模并行的I&F神经元VLSI网络，以模拟实时复杂的基于尖峰的学习算法。
We present a mixed-mode analog/digital VLSI device comprising an array of leaky integrate-and-fire (I&F) neurons, adaptive synapses with spike-timing dependent plasticity, and an asynchronous event based communication infrastructure that allows the user to (re)con figure networks of spiking neurons with arbitrary topologies. The asynchronous communication protocol used by the silicon neurons to transmit spikes (events) off-chip and the silicon synapses to receive spikes from the outside is based on the "address-event representation" (AER). We describe the analog circuits designed to implement the silicon neurons and synapses and present experimental data showing the neuron's response properties and the synapses characteristics, in response to AER input spike trains. Our results indicate that these circuits can be used in massively parallel VLSI networks of I&F neurons to simulate real-time complex spike-based learning algorithms.