A 0.3–1.4 GHz All-Digital Fractional-N PLL With Adaptive Loop Gain Controller
A 0.3–1.4 GHz All-Digital Fractional-N PLL With Adaptive Loop Gain Controller
复制标题
具有自适应环路增益控制器的 0.3–1.4 GHz 全数字小数 N PLL
DOI：
--
复制
发表时间：
2010
影响因子：
5.4
通讯作者：
D. Jeong
中科院分区：
文献类型：
--
作者：
Deok;Heesoo Song;Taeho Kim;Suhwan Kim;D. Jeong
提出了一种0.3- 1.4GHz全数字锁相环（ADPLL），具有自适应环路增益控制器（ALGC）、1/8分辨率小数分频器和频率搜索模块。ALGC降低了开关式鉴频鉴相器（BBPFD）的非线性，从而降低了输出抖动。小数分频器部分补偿了小数N分频频率合成引起的大输入相位误差。使用伪位置方法的快速频率搜索单元在对应于192个参考时钟周期的6次迭代中实现频率锁定。采用0.13 μm CMOS逻辑工艺，设计了一个采用无死区重定时器的BBPFD、ALGC、小数分频器和频率搜索算法的数字逻辑实现的全数字锁相环（ADPLL）。该内核占用0.2 mm 2，功耗为16.5 mW，1.2V电源，1.35 GHz。在激活ALGC的情况下，实测RMS和峰峰值抖动分别为3.7 ps和32 ps。
A 0.3-1.4 GHz all-digital phase locked loop (ADPLL) with an adaptive loop gain controller (ALGC), a 1/8-resolution fractional divider and a frequency search block is presented. The ALGC reduces the nonlinearity of the bang-bang phase-frequency detector (BBPFD), reducing output jitter. The fractional divider partially compensates for the large input phase error caused by fractional-N frequency synthesis. A fast frequency search unit using the false position method achieves frequency lock in 6 iterations that correspond to 192 reference clock cycles. A prototype ADPLL using a BBPFD with a dead-zone-free retimer, an ALGC, a fractional divider, and a digital logic implementation of a frequency search algorithm was fabricated in a 0.13-μm CMOS logic process. The core occupies 0.2 mm2 and consumes 16.5 mW with a 1.2-V supply at 1.35-GHz. Measured RMS and peak-to-peak jitter with activating the ALGC are 3.7 ps and 32 ps respectively.