Development of a High-Level Simulation Approach and Its Application to Multicore Video Decoding
Development of a High-Level Simulation Approach and Its Application to Multicore Video Decoding
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DOI：
10.1109/tcsvt.2009.2031523
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发表时间：
2009-11
影响因子：
8.4
通讯作者：
F. Seitner;M. Bleyer;M. Gelautz;Ralf M. Beuschel
中科院分区：
文献类型：
--
作者：
F. Seitner;M. Bleyer;M. Gelautz;Ralf M. Beuschel
在本文中，我们介绍了一个高层次的模拟方法，多核视频处理架构的建模。该方法允许并行视频处理应用（VPA）的设计空间探索。它用于测试在任意虚拟硬件和软件配置上运行VPA的性能。该方法表示在现场可编程门阵列或专用集成电路上执行“完整”解码器实现的替代方案。因此，我们的方法的使用产生了相当多的时间，劳动力和成本效益的优点。作为一个应用程序，我们使用我们的方法来设计一个并行的H.264解码器，目标是720 p 25分辨率，比特率高达50 Mb/s。从单核解码器实现开始，我们使用我们的模拟器来估计使用多核架构时的性能增益。然后，我们检测这个多核系统中的主要性能瓶颈，并相应地执行额外的解码器拆分，直到我们达到目标要求。使用功能分裂（即，流水线）和数据并行处理。最终的H.264解码器架构能够满足我们的性能要求。
In this paper, we introduce a high-level simulation methodology for the modeling of multicore video processing architectures. This method allows design space explorations of parallel video processing applications (VPAs). It is used to test the performance of running a VPA on arbitrary virtual hardware and software configurations. The method represents an alternative to performing a "complete" decoder implementation on a field-programmable gate array or an application-specific integrated circuit. The use of our method, therefore, yields the advantage of being considerably more time, labor, and cost efficient. As an application, we use our method for designing a parallel H.264 decoder targeting 720 p 25 resolution at bit-rates up to 50 Mb/s. Starting from a single-core decoder implementation, we use our simulator for estimating the performance gain when using a multicore architecture. We then detect the major performance bottlenecks in this multicore system and perform additional decoder splittings accordingly until we reach the targeted requirements. The use of functional splitting (i.e., pipelining) and data-parallel processing is demonstrated. The final H.264 decoder architecture is capable of fulfilling our performance requirements.