FPGA Implementation of 3-bit Quantized CNN for Semantic Segmentation
FPGA Implementation of 3-bit Quantized CNN for Semantic Segmentation
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DOI：
10.1088/1742-6596/1729/1/012004
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发表时间：
2021-01
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通讯作者：
M. Miyama
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作者：
M. Miyama
语义分割是一种输入图像并对每个像素进行类别分类的任务。CNN的语义切分具有较高的准确率，但其使用浮点数的计算消耗了大量的能量。我们采用UNET作为CNN的语义切分方法，并对其进行了改进，使之适合于在FPGA上实现。我们将网络的权重和激活都量化到3比特。然后，我们为量化的CNN设计了一种专用的硬件结构，并在一片FPGA上实现了它。该电路仅使用内部存储器来执行前向传播计算，从而消除了高功率外部存储器访问。该电路是一种无失速逐个像素的流水线，并行执行8行、16个输入通道、16个输出通道、3x3像素的卷积计算。工作频率为300MHZ的卷积计算性能为11top/S。
Semantic segmentation is a task of inputting an image and performing category classification for each pixel. Semantic segmentation by CNN has high accuracy but its calculation using floating-point numbers consumes a large amount of power. We adopted UNET as the semantic segmentation CNN and improved it for FPGA implementation. We quantized both weights and activations of the network up to 3-bit. Then, we devised a dedicated hardware architecture for the quantized CNN and implemented it on an FPGA. This circuit uses only internal memory to perform forward propagation calculations, that eliminates high-power external memory accesses. This circuit is a stall-free pixel-by-pixel pipeline, and performs 8 rows, 16 input channels, 16 output channels, 3 by 3 pixels convolution calculations in parallel. The convolution calculation performance at an operating frequency of 300 MHz is 11 TOPs/s.