Cache Friendliness-Aware Managementof Shared Last-Level Caches for HighPerformance Multi-Core Systems
Cache Friendliness-Aware Managementof Shared Last-Level Caches for HighPerformance Multi-Core Systems
复制标题
高性能多核系统共享末级缓存的缓存友好性感知管理
DOI：
10.1109/tc.2013.18
复制
发表时间：
2014
影响因子：
3.7
通讯作者：
L. John
中科院分区：
文献类型：
--
作者：
Dimitris Kaseridis;M. Iqbal;L. John
为了实现高效率并防止多个分散的工作负载之间的破坏性干扰，芯片多处理器的末级缓存必须得到仔细的管理。先前提出的高速缓存管理方案存在高速缓存容量利用效率低下的问题，其要么侧重于提高高速缓存未命中的绝对数量，要么通过分配高速缓存容量而不考虑应用程序的存储器共享特性。未命中总数的减少并不总是与更高的性能相关，因为内存级并行可以隐藏无序执行中大量未命中的延迟损失。在这项工作中，我们描述了一种针对末级缓存的准分区方案，该方案结合了竞争应用的内存级并行性、缓存友好性和干扰敏感性，以有效地管理共享缓存容量。该方案提高了系统吞吐量和执行公平性，优于以往不受应用程序内存行为影响的方案。我们详细的全系统模拟表明，与四核CMP系统的次优方案相比，吞吐量平均提高了10%，公平性提高了9%。
To achieve high efficiency and prevent destructive interference among multiple divergent workloads, the last-level cache of Chip Multiprocessors has to be carefully managed. Previously proposed cache management schemes suffer from inefficient cache capacity utilization, by either focusing on improving the absolute number of cache misses or by allocating cache capacity without taking into consideration the applications' memory sharing characteristics. Reduction of the overall number of misses does not always correlate with higher performance as Memory-level Parallelism can hide the latency penalty of a significant number of misses in out-of-order execution. In this work we describe a quasi-partitioning scheme for last-level caches that combines the memory-level parallelism, cache friendliness and interference sensitivity of competing applications, to efficiently manage the shared cache capacity. The proposed scheme improves both system throughput and execution fairness - outperforming previous schemes that are oblivious to applications' memory behavior. Our detailed, full-system simulations showed an average improvement of 10 percent in throughput and 9 percent in fairness over the next best scheme for a four-core CMP system.