Automated Accelerator Optimization Aided by Graph Neural Networks
Automated Accelerator Optimization Aided by Graph Neural Networks
复制标题
图神经网络辅助的自动加速器优化
DOI：
10.1145/3490422.3502330
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发表时间：
2022
期刊：
影响因子：
--
通讯作者：
and Cong, Jason
中科院分区：
文献类型：
--
作者：
Sohrabizadeh, Atefeh;Bai, Yunsheng;Sun, Yizhou;and Cong, Jason
使用高级综合（HLS），硬件设计人员必须只描述设计的高级行为流程。然而，开发一个高性能的架构仍然需要几周的时间，主要是因为在更高的层次上有许多设计选择需要探索。此外，使用HLS工具评估设计需要几分钟到几个小时。为了解决这个问题，我们用一个图神经网络来模拟HLS工具，该网络经过训练可以用于广泛的应用。实验结果表明，我们的模型可以在毫秒内以高精度估计设计的质量，与以前依赖HLS工具的最先进的工作相比，优化设计的速度提高了79倍（平均48倍）。
Using High-Level Synthesis (HLS), the hardware designers must describe only a high-level behavioral flow of the design. However, it still can take weeks to develop a high-performance architecture mainly because there are many design choices at a higher level to explore. Besides, it takes several minutes to hours to evaluate the design with the HLS tool. To solve this problem, we model the HLS tool with a graph neural network that is trained to be used for a wide range of applications. The experimental results demonstrate that our model can estimate the quality of design in milliseconds with high accuracy, resulting in up to 79X speedup (with an average of 48X) for optimizing the design compared to the previous state-of-the-art work relying on the HLS tool.