Time-domain macromodels for VLSI interconnect analysis
Time-domain macromodels for VLSI interconnect analysis
复制标题
用于 VLSI 互连分析的时域宏模型
DOI：
10.1109/43.317469
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发表时间：
1994
期刊：
影响因子：
--
通讯作者：
L. Pileggi
中科院分区：
文献类型：
--
作者：
Seok;N. Gopal;L. Pileggi
本文提出了一种获得用于电路仿真的VLSI互连网络时域宏模型的方法。这项工作的目标是尽可能有效地在电路仿真中包含互连寄生效应，而不显着影响精度。还讨论了稳定性问题和合并传输线互连的增强。描述了一个统一的电路仿真框架，该框架结合了不同类别的互连并基于所提出的宏模型。通过使用 RC 和 RLC 互连的示例证明了宏模型的简单性和通用性。 >
This paper presents a method of obtaining time-domain macromodels of VLSI interconnection networks for circuit simulation. The goal of this work is to include interconnect parasitics in a circuit simulation as efficiently as possible, without significantly compromising accuracy. Stability issues and enhancements to incorporate transmission line interconnects are also discussed. A unified circuit simulation framework, incorporating different classes of interconnects and based on the proposed macromodels, is described. The simplicity and generality of the macromodels is demonstrated through examples employing RC- and RLC-interconnects. >