GaAs FET characterization in a quasi-monolithic Si environment
GaAs FET characterization in a quasi-monolithic Si environment
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准单片 Si 环境中的 GaAs FET 表征
DOI：
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发表时间：
1999
期刊：
影响因子：
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通讯作者：
P. Hudek
中科院分区：
文献类型：
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作者：
E. Wasige;G. Kompa;F. van Raay;W. Scholz;I. Rangelow;R. Kassing;S. Bertram;P. Hudek
GaAs FET芯片是平面嵌入在高电阻率硅衬底和其特征在于高达40 GHz的共面环境。混合互连（键合线）被薄膜互连（空气桥）所取代。小信号等效电路提取结果证实了预期的低寄生电感值。这些减少了超过50%的典型键合线互连。
GaAs FET chips are planar embedded in a high resistivity silicon substrate and characterized up to 40 GHz in a coplanar environment. Hybrid interconnects (bonding wires) are replaced by thin film ones (air bridges). Small signal equivalent circuit extraction results confirm the expected low parasitic inductance values. These are reduced by more than 50% of the typical bonding wire interconnects.