Diagnosis for Bridging Faults on Clock Lines
Diagnosis for Bridging Faults on Clock Lines
复制标题
时钟线桥接故障诊断
DOI:
10.1109/prdc.2012.15
复制
发表时间:
2012
期刊:
影响因子:
--
通讯作者:
S. Kobayashi and K. Saluja
中科院分区:
文献类型:
--
作者:
Y. Higami;H. Takahashi;S. Kobayashi and K. Saluja
This paper presents diagnosis methods for bridging faults between a clock line and a gate signal line. Scan-based simulation methods are applied while assuming that only scan-based flush tests are used. In view of the fact that initial states play an important role, we consider two possible scenarios: 1) all flip-flops are assumed to be reset table, and 2) flip-flops are not reset table. In order to handle unknown states due to the non-reset table flip-flops, we introduce heuristic techniques. The effectiveness of the proposed methods are evaluated by the experimental results for benchmark circuits.