A Fully Integrated Multistage Cross-Coupled Voltage Multiplier With No Reversion Power Loss in a Standard CMOS Process
A Fully Integrated Multistage Cross-Coupled Voltage Multiplier With No Reversion Power Loss in a Standard CMOS Process
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完全集成的多级交叉耦合电压倍增器，采用标准 CMOS 工艺，无反向功率损耗
DOI：
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发表时间：
2017
期刊：
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通讯作者：
Jie Chen
中科院分区：
文献类型：
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作者：
Xiaojian Yu;K. Moez;I;M. Sawan;Jie Chen
本简报介绍了一款用于升压DC-DC转换器应用的全集成交叉耦合电压倍增器。提出的设计采用了一种新的交叉耦合倍压器（CCVD）结构和时钟方案，消除了所有的反向功率损耗，提高了电源效率（PE）。此外，由于最大栅源/漏或漏源电压不超过标称电源<inline-formula><tex-math notation="LaTeX">$V_mathrm{dd}$，因此</tex-math></inline-formula>该设计可扩展为多级倍压器（电压倍增器）。因此，这种设计与标准CMOS工艺兼容，没有任何过应力电压。所提出的单级CCVD和三级交叉耦合电压倍增器在0.13-<inline-formula><tex-math notation="LaTeX">$mu ext{m}$</tex-math></inline-formula>IBM CMOS工艺，最大PE值分别为88.16%和80.2%。在1.2V电源电压下，最大电压转换效率达到99.8%。
This brief presents a fully integrated cross-coupled voltage multiplier for boosting dc-to-dc converter applications. The proposed design applies a new structure of cross-coupled voltage doubler (CCVD) and a clock scheme that eliminates all of the reversion power loss and increases the power efficiency (PE). In addition, this design is scalable to multiple-stage voltage doubler (voltage multiplier) as the maximum gate-to-source/drain or drain-to-source voltage does not exceed the nominal power supply <inline-formula><tex-math notation="LaTeX">$V_mathrm{dd}$</tex-math></inline-formula>. As a result, such a design is compatible with the standard CMOS process without any overstress voltage. The proposed single-stage CCVD and three-stage cross-coupled voltage multiplier are implemented in 0.13-<inline-formula><tex-math notation="LaTeX">$mu ext{m}$</tex-math></inline-formula> IBM CMOS process with maximum PE values of 88.16% and 80.2%, respectively. The maximum voltage conversion efficiency reaches 99.8% under the supply voltage of 1.2 V.