A Comprehensive Side-Channel Information Leakage Analysis of an In-Order RISC CPU Microarchitecture
A Comprehensive Side-Channel Information Leakage Analysis of an In-Order RISC CPU Microarchitecture
复制标题
有序 RISC CPU 微架构的全面侧通道信息泄漏分析
DOI：
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发表时间：
2018
期刊：
影响因子：
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通讯作者：
W. Fornaciari
中科院分区：
文献类型：
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作者：
Davide Zoni;Alessandro Barenghi;Gerardo Pelosi;W. Fornaciari
侧信道攻击是嵌入式系统安全的一大威胁。为了执行这些操作，攻击者会评估一组依赖密钥的功耗模型与从实际设备获取的一组侧信道测量值的拟合程度，并将密钥值标识为产生最佳拟合模型的密钥值。在这项工作中，我们首次分析了32位有序RISC CPU的微架构组件，显示了其中一个组件负责意外的侧信道信息泄漏。我们对泄漏源进行分类，识别微架构中的数据序列化点，并提供一组提示，可以有效地利用这些提示来生成抵抗侧信道攻击的实现，无论是编写还是生成适当的汇编代码。
Side-channel attacks are a prominent threat to the security of embedded systems. To perform them, an adversary evaluates the goodness of fit of a set of key-dependent power consumption models to a collection of side-channel measurements taken from an actual device, identifying the secret key value as the one yielding the best-fitting model. In this work, we analyze for the first time the microarchitectural components of a 32-bit in-order RISC CPU, showing which one of them is accountable for unexpected side-channel information leakage. We classify the leakage sources, identifying the data serialization points in the microarchitecture and providing a set of hints that can be fruitfully exploited to generate implementations resistant against side-channel attacks, either writing or generating proper assembly code.