Inherently linear capacitor error-averaging techniques for pipelined A/D conversion
Inherently linear capacitor error-averaging techniques for pipelined A/D conversion
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用于流水线 A/D 转换的固有线性电容器误差平均技术
DOI：
10.1109/82.826750
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发表时间：
2000
期刊：
影响因子：
--
通讯作者：
Y. Chiu
中科院分区：
文献类型：
--
作者：
Y. Chiu
提出了一种新的流水线模数转换无源电容失配误差平均技术。该架构固有的出色线性度有效地消除了电容器匹配要求，该电容器匹配要求防止常规单片流水线模数转换器在没有微调和/或校准的情况下达到10位及以上的积分非线性（INL）。仿真结果证实了观察和14位INL的情况下实现了7位电容匹配。宽松的匹配要求使得电容器尺寸能够按比例缩小到KT/C极限。结果，可以实现功耗和芯片面积的极大降低。
New passive capacitor mismatch error-averaging techniques for pipelined analog-to-digital conversion is presented. The excellent linearity inherent to the architecture effectively eliminates the capacitor matching requirement that prevents a conventional monolithic pipelined analog-to-digital converter from reaching a 10-bit and above integral nonlinearity (INL) without trimming and/or calibration. Simulation results confirm the observation and a case of 14 bit INL realized by 7 bit capacitor matching is shown. The relaxed matching requirement enables the scale-down of the capacitor sizes to that of the KT/C limit. As a result, great reductions in both power consumption and chip area can be achieved.