Statistical variability and reliability in nanoscale FinFETs
Statistical variability and reliability in nanoscale FinFETs
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DOI：
10.1109/iedm.2011.6131494
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发表时间：
2011-12
期刊：
影响因子：
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通讯作者：
Xingsheng Wang;A. Brown;B. Cheng;A. Asenov
中科院分区：
文献类型：
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作者：
Xingsheng Wang;A. Brown;B. Cheng;A. Asenov
本文对栅极长度分别为20nm、14nm和10nm、低通道掺杂的SOI衬底上新兴的缩放finfet的统计变异性和可靠性进行了全面的三维仿真研究。优秀的静电完整性和由此产生的对低通道掺杂的耐受性被认为是FinFET的主要优势，从而大大减少了随机离散掺杂（RDD）造成的统计变异性。研究发现，线边缘粗糙度（LER）、金属栅粒度（MGG）和界面捕获电荷（ITC）主导了器件的参数波动，并具有不同的分布特征，而RDD可能导致器件特性发生相对罕见但显著的变化。
A comprehensive full-scale 3D simulation study of statistical variability and reliability in emerging, scaled FinFETs on SOI substrate with gate-lengths of 20nm, 14nm and 10nm and low channel doping is presented. Excellent electrostatic integrity and resulting tolerance to low channel doping are perceived as the main FinFET advantages, resulting in a dramatic reduction of statistical variability due to random discrete dopants (RDD). It is found that line edge roughness (LER), metal gate granularity (MGG) and interface trapped charges (ITC) dominate the parameter fluctuations with different distribution features, while RDD may result in relatively rare but significant changes in the device characteristics.