A 2.6-V, 44-MHz all-digital QPSK direct-sequence spread-spectrum transceiver IC [wireless LANs]
A 2.6-V, 44-MHz all-digital QPSK direct-sequence spread-spectrum transceiver IC [wireless LANs]
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2.6V、44MHz 全数字 QPSK 直序扩频收发器 IC [无线 LAN]
DOI：
10.1109/4.634658
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发表时间：
1997
期刊：
影响因子：
--
通讯作者：
T. Chiueh
中科院分区：
文献类型：
--
作者：
Jen;M. Liou;Hsi;T. Chiueh
提出了一种全数字差分编码四元相移键控（DEQPSK）直接序列扩频（DSSS）收发器。收发器由基带/中频扩频发射机和相干中频接收机两部分组成。该中频接收机的中心频率为11mhz，采样率为44msamples /s。调制/解调，载波恢复，PN采集和差分编码都在单个芯片内提供。在布局实现之前进行了功能优化和体系结构设计。0.8-/spl mu/m n阱CMOS芯片具有56000个晶体管的复杂性，核心面积为3.5/spl倍/3.5 mm/sup / 2/。在2.6 V和3.3 V电压下，功耗分别为92和145 mW。
In this paper, an all-digital differentially encoded quaternary phase shift keying (DEQPSK) direct sequence spread-spectrum (DSSS) transceiver is proposed. The transceiver consists of two parts: a baseband/IF spread-spectrum transmitter and a coherent intermediate frequency (IF) receiver. The center frequency of this IF receiver is 11 MHz and the sampling rate is 44 Msamples/s. Modulation/demodulation, carrier recovery, PN acquisition, and differential coding are all provided within a single chip. Functional optimization and architecture design were performed before layout implementation. The 0.8-/spl mu/m N-well CMOS chip has a complexity of 56000 transistors with a core area of 3.5/spl times/3.5 mm/sup 2/. Power dissipation is 92 and 145 mW at 2.6 and 3.3 V, respectively.