Steerable-Discrete-Cosine-Transform (SDCT): Hardware Implementation and Performance Analysis
Steerable-Discrete-Cosine-Transform (SDCT): Hardware Implementation and Performance Analysis
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DOI：
10.3390/s20051405
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发表时间：
2020-03-01
期刊：
影响因子：
3.9
通讯作者：
Martina, Maurizio
中科院分区：
文献类型：
--
作者：
Peloso, Riccardo;Capra, Maurizio;Martina, Maurizio
在过去的几年中，随着帧分辨率的急剧提高，对新的高效视频压缩方法的需求迅速增长。视频编码联合协作小组（JCT-VC）于2013年制定了H.265/高效视频编码（HEVC）标准，该标准代表了视频编码标准的最新水平。然而，在过去的几年里，人们提出了新的算法和技术来提高编码效率。一种有前途的方法依赖于将方向能力嵌入到转换阶段。近年来，人们提出了可转向离散余弦变换（SDCT），利用具有不同取向角的基来开发定向余弦变换。SDCT产生了更稀疏的表示，从而提高了编码效率。初步结果表明，SDCT可以嵌入到HEVC标准中，提供更好的压缩比。本文提出了一种SDCT的硬件结构，它能够在188MHz的频率下工作，吞吐量达到3.00 GSample/s。特别是，该架构支持帧率为60hz的8k超高清（UHD） （7680 x 4320），这是HEVC支持的最佳分辨率之一。
In the last years, the need for new efficient video compression methods grown rapidly as frame resolution has increased dramatically. The Joint Collaborative Team on Video Coding (JCT-VC) effort produced in 2013 the H.265/High Efficiency Video Coding (HEVC) standard, which represents the state of the art in video coding standards. Nevertheless, in the last years, new algorithms and techniques to improve coding efficiency have been proposed. One promising approach relies on embedding direction capabilities into the transform stage. Recently, the Steerable Discrete Cosine Transform (SDCT) has been proposed to exploit directional DCT using a basis having different orientation angles. The SDCT leads to a sparser representation, which translates to improved coding efficiency. Preliminary results show that the SDCT can be embedded into the HEVC standard, providing better compression ratios. This paper presents a hardware architecture for the SDCT, which is able to work at a frequency of 188MHz, reaching a throughput of 3.00 GSample/s. In particular, this architecture supports 8k UltraHigh Definition (UHD) (7680 x 4320) with a frame rate of 60 Hz, which is one of the best resolutions supported by HEVC.