Significant Enhancement of High-N s electron mobility in Ge n-MOSFETs
Significant Enhancement of High-N s electron mobility in Ge n-MOSFETs
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发表时间：
2013
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通讯作者：
C. Lu;T. Tabata;T. Nishimura;K. Nagashio;A. Toriumi
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作者：
C. Lu;T. Tabata;T. Nishimura;K. Nagashio;A. Toriumi
[引言] GeO 2基MOS技术的最新进展在实现高性能Ge CMOS方面引起了相当大的关注。目前，Ge n-MOSFET中最大的问题之一是，与Ge p-MOSFET中的空穴迁移率不同，高Ns区的电子迁移率显示出显著的退化[1]。在这项工作中，我们提出了显着的提高高Ns电子迁移率的亚纳米EOT Ge n-MOSFET的Y2 O3和低温高压氧化（LT-HPO）的组合，并讨论了可能的机制，电子迁移率的增强。[实验]将pGe（100）和（111）晶片用于MOSFET制造。定义了几种沟道长度（W/L = 25 μ m/100-500 μ m），并通过缓冲层以70 keV注入磷（1 × 107/cm剂量）以形成源极/漏极。对于栅极叠层形成，通过射频溅射沉积1.5 nm厚的Y2 O3，并在70 atm O2环境中在500 ℃下进行LT-HPO 60秒。0.7 LT-HPO后，在Ge/Y2 O3叠层上生长了nm厚的GeO 2界面层。总EOT由LT-HPO时间控制。Al被沉积并图案化用于栅极和源极/漏极接触。[结果和讨论]图1示出了作为EOT的函数的高Ns电子迁移率的基准。在具有亚nm EOT的Ge n-MOSFET中，证明了429 cm /Vs的高Ns迁移率，这是迄今为止规模化EOT Si [2]和Ge MOSFET [3-5]中最高的迁移率。值得注意的是，与纯Ge/GeO 2叠层相比，高Ns区的电子迁移率显著增强。值得注意的是，与纯Ge/GeO 2叠层相比，高Ns区的电子迁移率显著增强。为了理解高Ns区电子迁移率增强的原因，我们应该考虑Ge中的氧化过程。图2示出了Ge中的热氧化的示意图。众所周知，GeO 2的粘性流动发生在相对较高的温度（> 500 ℃）[6]。因此，在Ge氧化过程中，GeO 2的形成和氧空位（VO）的形成以及GeO 2的结构弛豫应同时考虑。为了释放界面应力，可能会发生短程有序（SRO）粗糙度的增加。然而，低温（LT）抑制粘性流动，HPO抑制VO的形成。因此，氧化速率极低[8]，导致SRO粗糙度显著降低。GeO 2中Y原子的混合可以进一步抑制VO的形成，导致粗糙度进一步降低，并且具有LT-HPO的Ge/GeOx/Y2 O3堆叠中的高Ns电子迁移率显著增强。[参考文献] [1] H. Lee等人，IEDM，416，2010. [2]T. Kawango等人，TED，59，269，2012. [3]S. Takagi等人，IEDM，505，2012. [4]W. B。Chen等人，IEDM，420，2010年。[5]C.- M. Lin等人，IEDM，509，2012. [6]M. I. Ozhovan，JETP，103，819，2006. [7]S. K. Wang等人，JAP，108，054104，2010。[8]C. H. Lee等人，APEX，5，114001，2012。
[Introduction] Recent progress of GeO2-based MOS technology has attracted considerable attention in realization of high performance Ge CMOS beyond Si. One of the great concerns in Ge n-MOSFETs now is that electron mobility shows a substantial degradation in high-Ns region, unlike hole mobility in Ge p-MOSFETs [1]. In this work, we present the significant enhancement of high-Ns electron mobility in sub-nm EOT Ge n-MOSFETs by the combination of Y2O3 and low-temperature high-pressure oxidation (LT-HPO), and possible mechanisms of electron mobility enhancement is discussed. [Experiment] pGe(100) and (111) wafers were used for MOSFETs fabrication. Several channel lengths (W/L = 25 m/100-500 m) were defined, and phosphorus (1x10 /cm dose) was implanted at 70 keV through the buffer layer for source/drain formation. For gate stack formation, 1.5 nm-thick Y2O3 was deposited by rf-sputtering and LT-HPO was carried out at 500C for 60 sec in 70 atm O2 ambient. 0.7 nm-thick GeO2 interfacial layer was grown at Ge/Y2O3 stack after LT-HPO. The total EOT was controlled by LT-HPO time. Al was deposited and patterned for the gate and source/drain contacts. [Results and Discussion] Fig. 1 shows the benchmark of the high-Ns electron mobility as a function of EOT. The high-Ns mobility of 429 cm /Vs in Ge n-MOSFETs with sub-nm EOT is demonstrated, which is the highest one to date among scaled EOT Si [2] and Ge MOSFETs [3-5]. It is worthy note that electron mobility in high-Ns region is significantly enhanced, compared to pure Ge/GeO2 stack. It is worthy note that electron mobility in high-Ns region is significantly enhanced, compared to pure Ge/GeO2 stack. In order to understand the origin of electron mobility enhancement in high-Ns region, we should consider oxidation process in Ge. Fig. 2 shows a schematic of thermal oxidation in Ge. It is well known that viscous flow of GeO2 occurs at relatively high temperature (> 500C) [6]. Therefore, in Ge oxidation process, GeO2 formation and the oxygen vacancy (VO) formation as well as structural relaxation of GeO2 should be considered simultaneously. In order to release the interface stress, an increase of short-range order (SRO)-roughness is likely to occur. However, low-temperature (LT) suppresses the viscous flow and HPO suppresses VO formation thermodynamically [7]. Thus, oxidation rate is extremely low [8], resulting in a significant reduction of SRO-roughness. The intermixed Y atoms in GeO2 can further suppress the VO formation resulting in further reduction of roughness, and high-Ns electron mobility in Ge/GeOx/Y2O3 stack with LT-HPO is dramatically enhanced. [Reference] [1] C. H. Lee et al., IEDM, 416, 2010. [2] T. Kawango et al., TED, 59, 269, 2012. [3] S. Takagi et al., IEDM, 505, 2012. [4] W. B. Chen et al., IEDM, 420, 2010. [5] C.-M. Lin et al., IEDM, 509, 2012. [6] M. I. Ozhovan, JETP, 103, 819, 2006. [7] S. K. Wang et al., JAP, 108, 054104, 2010. [8] C. H. Lee et al., APEX, 5, 114001, 2012.