Investigations on Line-Edge Roughness (LER) and Line-Width Roughness (LWR) in Nanoscale CMOS Technology: Part II–Experimental Results and Impacts on Device Variability
Investigations on Line-Edge Roughness (LER) and Line-Width Roughness (LWR) in Nanoscale CMOS Technology: Part II–Experimental Results and Impacts on Device Variability
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DOI：
10.1109/ted.2013.2283517
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发表时间：
2013-10
影响因子：
3.1
通讯作者：
Runsheng Wang;Xiaobo Jiang;Tao Yu;Jiewen Fan;Jiang Chen;D. Pan;Ru Huang
中科院分区：
文献类型：
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作者：
Runsheng Wang;Xiaobo Jiang;Tao Yu;Jiewen Fan;Jiang Chen;D. Pan;Ru Huang
在本文的第一部分中，通过理论建模和仿真研究了线边缘粗糙度（LER）和线宽粗糙度（LWR）之间的相关性。本文研究了 LER 和 LWR 之间相关性的过程依赖性。实验结果表明，Si Fin和纳米线都具有强相关的LER/LWR，并且两个边缘的互相关性取决于制造工艺。基于本文第一部分提出的改进仿真方法，研究了相关LER/LWR对双栅器件沟道的影响。结果表明，Vth分布强烈依赖于互相关，并且可以表现出非高斯分布和/或多峰分布，从而放大了Vth变化。
In the part I of this paper, the correlation between line-edge roughness (LER) and line-width roughness (LWR) is investigated by theoretical modeling and simulation. In this paper, process-dependence of the correlation between LER and LWR is studied. The experimental results indicate that both Si Fin and nanowire have strongly correlated LER/LWR, and the cross-correlation of two edges depends on the fabrication process. Based on the improved simulation method proposed in the Part I of this paper, the impacts of correlated LER/LWR in the channel of double-gate devices are investigated. The results show that Vth distribution strongly relies on cross-correlation, and can exhibit non-Gaussian distribution and/or multipeak distribution, which enlarges the Vth variation.