New three-dimensional integration technology using chip-to-wafer bonding to achieve ultimate super-chip integration
New three-dimensional integration technology using chip-to-wafer bonding to achieve ultimate super-chip integration
复制标题
DOI：
10.1143/jjap.45.3030
复制
发表时间：
2006-04-01
期刊：
影响因子：
--
通讯作者：
Koyanagi, Mitsumasa
中科院分区：
文献类型：
--
作者：
Fukushima, Takafumi;Yamada, Yusuke;Koyanagi, Mitsumasa
一种新的三维（3D）集成技术，使用芯片到晶片键合技术提供了最终的超级芯片集成，其中不同尺寸的各种芯片可以垂直堆叠并通过多个垂直互连进行电连接。我们已经研究了几个关键技术的垂直互连形成，芯片对准，芯片到晶圆键合，粘合剂注入，和芯片减薄垂直堆叠已知良好的模具（KGD）到3D LSI芯片。通过使用这些关键技术，成功地制作了三维LSI测试芯片的垂直互连组成的In-Au微凸点和埋互连填充多晶硅（poly-Si）。测试芯片是由三种非常薄的芯片的5，6，和7毫米2和范围内的厚度从30到90微米。每个芯片都使用低粘度环氧树脂粘合剂作为介电材料紧密粘合。
A new three-dimensional (3D) integration technology using the chip-to-wafer bonding technique provides the ultimate super-chip integration in which various kinds of chip of different sizes can be vertically stacked and electrically connected through a number of vertical interconnections. We have investigated several key technologies of vertical interconnection formation, chip alignment, chip-to-wafer bonding, adhesive injection, and chip thinning to vertically stack known good dies (KGDs) into 3D LSI chips. By using these key technologies, successful fabrication of 3D LSI test chips with vertical interconnections consisting of In-Au microbumps and buried interconnections filled with polycrystalline silicon (poly-Si) was demonstrated. The test chips was composed of three kinds of very thin chip of 5, 6, and 7 mm 2 and ranging in thickness from 30 to 90 pm. Each chip is tightly bonded using a low-viscosity epoxy adhesive as a dielectric material.