A Variable Delay Line Phase Locked Loop For Cpu-coprocessor Synchronization
A Variable Delay Line Phase Locked Loop For Cpu-coprocessor Synchronization
复制标题
用于CPU-协处理器同步的可变延迟线锁相环
DOI：
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发表时间：
1988
期刊：
影响因子：
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通讯作者：
E. Hudson
中科院分区：
文献类型：
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作者：
M. Johnson;E. Hudson
随着微处理器频率的不断增加，芯片到芯片的连接速度也必须向上扩展，更严格的I/O时序要求意味着不能再容忍大的时钟缓冲延迟（以及相关的芯片到芯片时序不确定性）。因此，有必要将芯片时钟与全局参考信号同步。在本文发表后不久，片上时钟同步技术在大多数微处理器工业中被广泛采用。
AS MICROPROCESSOR frequencies continued to increase, chip-to-chip connection speeds also had to scale upwards, and more stringent I/O timing requirements meant that large clock buffer delays (and the associated chip-to-chip timing uncertainties) could no longer be tolerated. Therefore, it became necessary to synchronize the chip clock with a global reference signal. Soon after this paper, on-chip clock synchronization techniques were adopted in a widespread fashion across most of the microprocessor industry.