A low-power soft error tolerant latch scheme
A low-power soft error tolerant latch scheme
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DOI：
10.1109/asicon.2015.7516885
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发表时间：
2015-11
期刊：
影响因子：
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通讯作者：
Saki Tajima;Youhua Shi;N. Togawa;M. Yanagisawa
中科院分区：
文献类型：
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作者：
Saki Tajima;Youhua Shi;N. Togawa;M. Yanagisawa
随着工艺技术的不断扩展，集成电路的低功耗和可靠性变得比以往任何时候都更加重要。特别是，由于节点电容和工作电压的降低以实现低功耗，这使得电路对高能粒子引起的软错误更加敏感。本文提出了一种低功耗的软容错锁存器TSPC-SEH。仿真结果表明，所提出的TSPC-SEH锁存器可以实现高达42%的功耗降低和54%的延迟改善相比，现有的软容错SEH和DICE设计。
As process technology continues scaling, low power and reliability of integrated circuits are becoming more critical than ever before. Particularly, due to the reduction of node capacitance and operating voltage for low power consumption, it makes the circuits more sensitive to high-energy particles induced soft errors. In this paper, a soft-error tolerant latch called TSPC-SEH is proposed for soft error tolerance with low power consumption. The simulation results show that the proposed TSPC-SEH latch can achieve up to 42% power consumption reduction and 54% delay improvement compared to the existing soft error tolerant SEH and DICE designs.