Multi-cell soft errors at the 16-nm FinFET technology node
Multi-cell soft errors at the 16-nm FinFET technology node
复制标题
16 nm FinFET 技术节点的多单元软错误
DOI：
10.1109/irps.2015.7112730
复制
发表时间：
2015
期刊：
影响因子：
--
通讯作者：
I. Chatterjee
中科院分区：
文献类型：
--
作者：
N. Tam;B. Bhuva;L. Massengill;D. Ball;M. Mccurdy;M. Alles;I. Chatterjee
采用重离子对采用商业体CMOS工艺制造的16 nm FinFET SRAM设计的软错误性能进行了评估。包括电源电压变化的结果表明，多单元翻转占主导地位的软错误率。双端口SRAM具有比单端口SRAM更高的横截面，但在位线方向上没有任何多单元翻转。TCAD模拟显示作为粒子LET的函数的电参数的扰动的程度支持实验数据。
Soft error performance of 16-nm FinFET SRAM designs fabricated using a commercial bulk CMOS process is evaluated using heavy-ions. Results included supply voltage variations show that multi-cell upsets dominate soft-error rates. Dual-port SRAM has higher cross-section than single-port SRAM but did not have any multi-cell upset across the bit-line direction. TCAD simulations showing the extent of the perturbation in the electric parameters as a function of particle LET support the experimental data.