Bidirectional Peripheral Nerve Interface With 64 Second-Order Opamp-Less ΔΣ ADCs and Fully Integrated Wireless Power/Data Transmission
Bidirectional Peripheral Nerve Interface With 64 Second-Order Opamp-Less ΔΣ ADCs and Fully Integrated Wireless Power/Data Transmission
复制标题
具有 64 个二阶无运算放大器 ΔΣ ADC 和完全集成无线电源/数据传输的双向周围神经接口
DOI：
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发表时间：
2021
影响因子：
5.4
通讯作者：
R. Genov
中科院分区：
文献类型：
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作者：
Maged ElAnsary;Jianxiong Xu;José B. Sales Filho;Gairik Dutta;Liam Long;Camilo Tejeiro;Aly Shoukry;Chenxi Tang;Enver G. Kilinc;Jaimin Joshi;P. Sabetian;Samantha Unger;J. Zariffa;P. Yoo;R. Genov
介绍了一种用于与周围神经接口的有源探针和微刺激器SoC。它进行经络耐伪迹神经记录，阻抗传感补偿袖带不平衡，以及闭环系统操作的神经刺激。每个记录通道是消耗140 nW并且在130 nm的CMOS中占据0.01 mm面积的二阶运算公式直插式ADC。单环路<；内联公式&>lt；tex-ath NOTATION=“LaTeX”>；$Delta Sigma$<；//内联-公式&>架构使用两个无源积分器实现二阶噪声整形。就我们所知，这产生了任何二阶<；内联公式>；<；tex-ath notation=“LaTeX”>；$Delta Sigma$<；/特克斯-数学&><；/内联-公式&>ADC和最低FOM(fj/conv.步骤)任何无源二阶<；内联公式&><；tex-ath notation=“LaTeX”&>$Delta Sigma$<；//内联-公式&>ADC(27 FJ/conv.步骤)。SoC独特地执行多模式输入信号记录：使用频率多路复用法同时测量电压(用于神经记录)和电流(用于阻抗检测)。SoC还具有60 MHz高能效感应电源链路和600 MHz射频数据通信链路。该样机在大鼠坐骨神经上进行了体内验证，用于神经电信号(ENG)的传感和袖带电极阻抗失衡的校正。
An active probe and microstimulator SoC for interfacing with peripheral nerves is presented. It performs 64-channel artifact-tolerant neural recording, cuff imbalance compensation by impedance sensing, and neurostimulation for the closed-loop operation. Each recording channel is a second-order opamp-less <inline-formula> <tex-math notation="LaTeX">$Delta Sigma $ </tex-math></inline-formula> ADC that consumes 140 nW and occupies 0.01 mm<sup>2</sup> area in 130 nm CMOS. The single-loop <inline-formula> <tex-math notation="LaTeX">$Delta Sigma $ </tex-math></inline-formula> architecture achieves second-order noise shaping with two passive integrators. To the best of our knowledge, this yields the lowest power and area of any second-order <inline-formula> <tex-math notation="LaTeX">$Delta Sigma $ </tex-math></inline-formula> ADC and the lowest FOM (fJ/conv. step) of any passive second-order <inline-formula> <tex-math notation="LaTeX">$Delta Sigma $ </tex-math></inline-formula> ADC (27 fJ/conv. step). The SoC uniquely performs multi-modal input signal recording: voltage (for neural recording) and current (for impedance sensing) are measured concurrently using frequency multiplexing. The SoC also features a 60 MHz energy-efficient inductive powering link and a 600 MHz RF data communication link. The prototype is validated <italic>in vivo</italic> in the rat sciatic nerve for electroneurogram (ENG) sensing and the correction of impedance-imbalance in cuff electrodes.