HL-Pow: A Learning-Based Power Modeling Framework for High-Level Synthesis
HL-Pow: A Learning-Based Power Modeling Framework for High-Level Synthesis
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HL-Pow：用于高级综合的基于学习的功率建模框架
DOI：
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发表时间：
2020
期刊：
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通讯作者：
Wei Zhang
中科院分区：
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作者：
Zhe Lin;Jieru Zhao;Sharad Sinha;Wei Zhang
高级合成（HLS）使设计人员能够有效地自定义硬件设计。但是，预见到早期设计阶段的功耗与基于HLS的应用程序之间的相关性仍然是一项挑战。为了克服这个问题，我们介绍了HL-Pow，这是基于最先进的机器学习技术的FPGA HLS的功率建模框架。 HL-POW结合了自动化功能构造流，以有效地识别和提取功能，仅基于HLS结果，对功耗产生重大影响，以及可以建立适用于各种设计的准确且通用的功率模型的建模流量HLS。通过使用HL-POW，可以显着加快FPGA设计的功率评估过程，因为HL-POW的功率推断是在HLS上建立的，而不是耗时的寄存器转移级别（RTL）实现流。实验结果表明，HL-POW可以实现与机载电源测量相距仅4.67％（24.02 mW）的准确功率建模。为了进一步促进以电力为导向的优化，我们描述了一种新颖的设计空间探索（DSE）算法，建立在HL-POW之上，以在潜伏期和功耗之间进行权衡。该算法可以达到真正的帕累托边界的近似值，而只需要在整个设计空间中运行HLS流量20％。
High-level synthesis (HLS) enables designers to customize hardware designs efficiently. However, it is still challenging to foresee the correlation between power consumption and HLS-based applications at an early design stage. To overcome this problem, we introduce HL-Pow, a power modeling framework for FPGA HLS based on state-of-the-art machine learning techniques. HL-Pow incorporates an automated feature construction flow to efficiently identify and extract features that exert a major influence on power consumption, simply based upon HLS results, and a modeling flow that can build an accurate and generic power model applicable to a variety of designs with HLS. By using HL-Pow, the power evaluation process for FPGA designs can be significantly expedited because the power inference of HL-Pow is established on HLS instead of the time-consuming register-transfer level (RTL) implementation flow. Experimental results demonstrate that HL-Pow can achieve accurate power modeling that is only 4.67% (24.02 mW) away from onboard power measurement. To further facilitate power-oriented optimizations, we describe a novel design space exploration (DSE) algorithm built on top of HL-Pow to trade off between latency and power consumption. This algorithm can reach a close approximation of the real Pareto frontier while only requiring running HLS flow for 20% of design points in the entire design space.