A 124-Gb/s Decoder for Generalized Integrated Interleaved Codes

A 124-Gb/s Decoder for Generalized Integrated Interleaved Codes
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用于通用集成交错码的 124 Gb/s 解码器

DOI:
10.1109/tcsi.2019.2911730
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发表时间:
2019-04
期刊:
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS–I: REGULAR PAPERS
影响因子:
--
通讯作者:
Zhongfeng Wang
Zhongfeng Wang
中科院分区:
其他
文献类型:
--
作者:
Wenjie Li;Jun Lin;Zhongfeng Wang

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在分布式存储系统中,广义集成交织(GII)码可以通过创建交织共享的冗余度来减少总体冗余度,因此受到了广泛的关注。Berlekamp-Massey(BM)算法通过在每个译码阶段重复使用前面的结果来提高GII译码的效率。然而,它也构成了GII解码器的速度瓶颈。新提出的无逆Berlekamp-Massey(RiBM)算法以其关键路径短而著称,但由于其多项式难以直接重复使用,一般不适用于GII译码。在本文中,我们通过重新初始化多项式来解决这个问题,并提出了一种基于riBM的GII解码算法。在我们的模拟中,在高信噪比(SNR)区域观察到由于第一层错误校正而导致的轻微性能下降。因此,引入了一种微妙的方法来处理错校的交错。在此基础上,给出了该译码算法的硬件结构,并实现了一个高吞吐量的GII码译码实例。在台积电28 nm工艺下的综合结果表明,该解码器的吞吐量最高可达124 GB/S,并已在现场可编程门阵列中实现,以验证其纠错性能。
Generalized integrated interleaved (GII) codes have attracted much attention in distributed storage systems since they can reduce the overall redundancy by creating redundancy shared by the interleaves. The Berlekamp-Massey (BM) algorithm makes the GII decoding efficient by reusing the preceding results at each decoding stage. However, it also forms the speed bottleneck of GII decoders. The reformulated inversionless Berlekamp-Massey (riBM) algorithm is well known for its short critical path, but it is not generally suitable for GII decoding since its polynomials are difficult to be reused directly. In this paper, we address this issue by reinitializing the polynomials and propose a riBM-based GII decoding algorithm. In our simulations, slight performance degradation induced by the first-layer miscorrection is observed in the high signal-to-noise ratio (SNR) region. Hence, a subtle method is introduced to handle the miscorrected interleaves. Furthermore, the hardware architecture of the proposed decoding algorithm is developed and a high throughput decoder for the given example GII code is implemented. The synthesis results under TSMC 28-nm technology show that the decoder can achieve a throughput of up to 124 Gb/s. Moreover, the decoder has been implemented into a field-programmable gate array (FPGA) to validate its error-correction performance.
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