A novel SRAM-based FPGA architecture for efficient TMR fault tolerance support
A novel SRAM-based FPGA architecture for efficient TMR fault tolerance support
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一种新颖的基于 SRAM 的 FPGA 架构，可提供高效的 TMR 容错支持
DOI：
10.1109/fpl.2009.5272319
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发表时间：
2009
期刊：
影响因子：
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通讯作者：
D. Pnevmatikatos
中科院分区：
文献类型：
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作者：
Konstantinos Kyriakoulakos;D. Pnevmatikatos
本文提出了一种新的基于SRAM的FPGA架构，是适合映射设计时，容错是可取的。TMR已经成功地应用于FPGA中，以减轻瞬态故障，这可能发生在恶劣的环境中，如在空间应用中。此外，随着特征尺寸的缩小和电路可靠性的降低，容错技术变得越来越重要。然而，TMR带来高面积损失，其随着TMR晶粒变得更细而增加。我们建议对现有的基于SRAM的FPGA架构进行轻微修改，以支持细粒度冗余，面积成本甚至小于3倍（我们的基准电路平均为1.76倍）。我们的方法还提供了准确的故障定位，并允许更小，更不频繁的重新配置，节省重新配置的时间和功率。
This paper proposes a novel SRAM-based FPGA architecture that is suitable for mapping designs when fault tolerance is desirable. TMR has been successfully applied in FPGAs to mitigate transient faults, which are likely to occur in harsh environments such as in space applications. In addition, fault tolerance techniques gain importance as feature sizes shrink and make circuits less reliable. However, TMR comes at high area penalty, which increases as the TMR grain becomes finer. We propose a slight modification to existing SRAM-based FPGA architectures to support fine grain redundancy at an area cost even less than 3x (1.76 x in average for our benchmark circuits). Our approach also provides accurate fault location and allows smaller and more infrequent reconfigurations saving both reconfiguration time and power.