Mitigating and Tolerating Read Disturbance in STT-MRAM-Based Main Memory via Device and Architecture Innovations
Mitigating and Tolerating Read Disturbance in STT-MRAM-Based Main Memory via Device and Architecture Innovations
复制标题
通过器件和架构创新减轻和容忍基于 STT-MRAM 的主存储器中的读取干扰
DOI：
10.1109/tcad.2018.2878166
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发表时间：
2019
期刊：
影响因子：
--
通讯作者：
Lide Duan
中科院分区：
文献类型：
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作者：
Armin Haj Aboutalebi;Ethan C. Ahn;Bo Mao;Suzhen Wu;Lide Duan
作为一种重要的非易失性存储技术，自旋转移扭矩磁阻RAM(STT-MRAM)被广泛认为是未来处理器的通用存储解决方案。使用STT-MRAM作为主存储器提供了各种好处，但也带来了独特的设计挑战。具体地说，读干扰的特征是STT-MRAM在被读后意外地损坏数据，导致在每次读操作之后需要将数据恢复回存储器。在本文中，我们提出了器件和体系结构的创新来缓解和容忍读干扰。首先，我们定量地论证了读干扰与关键器件参数之间的关系，并提出了一些读干扰抑制方案。事实证明，这些设备级方案在降低读取干扰概率方面是有效的，但在其他设计指标上也会带来成本。因此，我们进一步提出了一种恢复感知的体系结构级别的存储控制器设计，以容忍读取干扰。由于读干扰带来的额外恢复极大地改变了传统存储控制器优化的时序场景，直接采用与恢复无关的DRAM存储管理技术将导致STT-MRAM的次优设计。因此，我们提出了恢复感知策略选择(RAP)，这是一种动态和混合的行缓冲区管理方案，它考虑了基于STT-MRAM的主存储器中不可避免的数据恢复。RIPS在运行时监视行缓冲区命中率，在两个静态页面关闭策略之间动态切换。通过将恢复考虑在内，RAP可准确捕获最佳设计点，从而在运行时实现最佳策略选择。我们的实验结果表明，与传统的页面关闭策略相比，RAP显著提高了系统性能和能效。
As an important nonvolatile memory technology, spin transfer torque magnetoresistive RAM (STT-MRAM) is widely considered as a universal memory solution for future processors. Employing STT-MRAM as the main memory offers a wide variety of benefits, but also results in unique design challenges. In particular, read disturbance characterizes accidental data corruption in STT-MRAM after it is read, leading to the need of restoring data back to memory after each read operation. In this paper, we propose both device and architecture innovations to mitigate and tolerate read disturbance. First, we quantitatively demonstrate the relationship between read disturbance and key device parameters, conducting a number of read disturbance mitigation schemes. These device-level schemes turn out to be effective in reducing the read disturbance probability, but come with costs on other design metrics. Consequently, we further propose a restore-aware memory controller design at the architecture level to tolerate read disturbance. Since the extra restores incurred by read disturbance greatly change the timing scenarios that conventional memory controllers were optimized for, directly adopting restore-agnostic DRAM memory management techniques will lead to suboptimal designs for STT-MRAM. Therefore, we propose restore-aware policy selection (RAPS), a dynamic and hybrid row buffer management scheme that factors in the inevitable data restores in STT-MRAM-based main memory. RAPS monitors the row buffer hit rate at run time, dynamically switching between two static page-closure policies. By factoring in restores, RAPS accurately captures the optimal design points, achieving optimal policy selections at run time. Our experimental results show that RAPS significantly improves system performance and energy efficiency compared to conventional page-closure policies.