Isolation Mechanisms for High-Speed Packet-Processing Pipelines
Isolation Mechanisms for High-Speed Packet-Processing Pipelines
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发表时间：
2021-01
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通讯作者：
Tao Wang;Xiangrui Yang;Gianni Antichi;Anirudh Sivaraman;Aurojit Panda
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作者：
Tao Wang;Xiangrui Yang;Gianni Antichi;Anirudh Sivaraman;Aurojit Panda
数据平面可编程性现在是主流。当我们发现更多用例时，部署需要能够在单个设备中运行多个数据包处理模块。这些可能是由独立团队在同一组织或多个组织中开发的。因此，我们需要隔离机制，以确保同一设备上的模块不会彼此干扰。本文介绍了Menshen，这是可重新配置匹配表（RMT）管道的扩展，该管道在不同的数据包处理模块之间实施了隔离。 Menshen由一组轻量级的硬件原始图和开源P4-16参考编译器的扩展，该参考编译器结合使用以实现此目标。我们在两个FPGA平台（NETFPGA和CORUNDUM）上进行了原型Menshen。我们表明我们的设计提供了隔离，并允许加载新模块而不会影响已经运行的模块。最后，我们证明，使用FreepDK45NM技术库和Synopsys DC合成软件在ASIC上实施Menshen的可行性，这表明我们的设计以1GHz时钟频率达到时间，并且需要大约6％的额外芯片区域。我们已经在https://isolation.quest/上为Menshen的硬件和软件开放了代码。
Data-plane programmability is now mainstream. As we find more use cases, deployments need to be able to run multiple packet-processing modules in a single device. These are likely to be developed by independent teams, either within the same organization or from multiple organizations. Therefore, we need isolation mechanisms to ensure that modules on the same device do not interfere with each other. This paper presents Menshen, an extension of the Reconfigurable Match Tables (RMT) pipeline that enforces isolation between different packet-processing modules. Menshen is comprised of a set of lightweight hardware primitives and an extension to the open source P4-16 reference compiler that act in conjunction to meet this goal. We have prototyped Menshen on two FPGA platforms (NetFPGA and Corundum). We show that our design provides isolation, and allows new modules to be loaded without impacting the ones already running. Finally, we demonstrate that feasibility of implementing Menshen on ASICs by using the FreePDK45nm technology library and the Synopsys DC synthesis software, showing that our design meets timing at a 1GHz clock frequency and needs approximately 6% additional chip area. We have open sourced the code for Menshen's hardware and software at https://isolation.quest/.