Low Dit high-k/In0.53Ga0.47As gate stack, with CET down to 0.73 nm and thermally stable silicide contact by suppression of interfacial reaction
Low Dit high-k/In0.53Ga0.47As gate stack, with CET down to 0.73 nm and thermally stable silicide contact by suppression of interfacial reaction
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低 Dit 高 k/In0.53Ga0.47As 栅极堆叠，CET 低至 0.73 nm，通过抑制界面反应实现热稳定硅化物接触
DOI：
10.1109/iedm.2013.6724544
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发表时间：
2013
期刊：
影响因子：
--
通讯作者：
H. Iwai
中科院分区：
文献类型：
--
作者：
D. Zadeh;H. Oomine;K. Kakushima;Y. Kataoka;A. Nishiyama;N. Sugii;H. Wakabayashi;K. Tsutsui;K. Natori;H. Iwai
采用La<sub>2</sub><sub>O3</sub>作为栅介质，成功地制备了CET= 0.73nm（EOT<0.5nm），D<sub>=</sub> 8.0×10<sup>11</sup>（cm<sup>-2</sup> eV<sup>-1</sup>还提出了一种在界面处具有良好可控性的硅化物/InGaAs结。这些结果保证了这种栅极堆叠对于未来节点3D器件结构的集成兼容性。
Ultra-thin InGaAs gate stacks with CET= 0.73 nm (EOT<; 0.5 nm), D<sub>it</sub> as low as 8.0×10<sup>11</sup> (cm<sup>-2</sup> eV<sup>-1</sup>) and thermal stability up to 600°C is demonstrated by using La<sub>2</sub>O<sub>3</sub> as gate dielectric. A silicide/InGaAs junction with excellent controllability at the interface is also proposed. These results promise the integration compatibility of this gate stack for future node 3D device structures.