Scan Shift Time Reduction Using Test Compaction for On-Chip Delay Measurement
Scan Shift Time Reduction Using Test Compaction for On-Chip Delay Measurement
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使用片上延迟测量的测试压缩来减少扫描移位时间
DOI：
10.1587/transinf.e97.d.533
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发表时间：
2014
期刊：
影响因子：
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通讯作者：
Hideo Ito
中科院分区：
文献类型：
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作者：
Wenpo Zhang;K. Namba;Hideo Ito
在目前的超大规模集成电路中，传统的延迟故障测试很难检测到小延迟缺陷，这会导致寿命短等严重问题。为了检测小延迟缺陷，提出了片上延迟测量方法，测量被测电路（CUT）中路径的延迟时间。然而，这种方法招致高的测试成本，因为它使用扫描设计，这带来了长的测试应用时间，由于扫描移位操作。我们的解决方案是一个测试应用程序的时间减少的方法，使用片上路径延迟测量测试。与传统的延迟测试不同，具有片上路径延迟测量的测试不需要捕获操作。具体地说，FF保持测试模式对的过渡模式，即使在测量p之后，也使测量下的路径（PUM）（表示为p）敏感。所提出的方法利用了这一特性。该方法通过测试模式合并减少了扫描移位时间和测试数据量。对ISCAS 89标准电路的测试结果表明，该方法减少了6.89 <$62.67%的测试时间和46.39 <$74.86%的测试数据量。关键词：小延迟缺陷，测试压缩，测试应用时间，测试数据量，片上延迟测量
In recent VLSIs, small-delay defects, which are hard to detect by traditional delay fault testing, can bring about serious issues such as short lifetime. To detect small-delay defects, on-chip delay measurement which measures the delay time of paths in the circuit under test (CUT) was proposed. However, this approach incurs high test cost because it uses scan design, which brings about long test application time due to scan shift operation. Our solution is a test application time reduction method for testing using the on-chip path delay measurement. The testing with on-chip path delay measurement does not require capture operations, unlike the conventional delay testing. Specifically, FFs keep the transition pattern of the test pattern pair sensitizing a path under measurement (PUM) (denoted as p) even after the measurement of p. The proposed method uses this characteristic. The proposed method reduces scan shift time and test data volume using test pattern merging. Evaluation results on ISCAS89 benchmark circuits indicate that the proposed method reduces the test application time by 6.89∼62.67% and test data volume by 46.39∼74.86%. key words: small-delay defects, test compaction, test application time, test data volume, on-chip delay measurement