Confidence Scalable Post-Silicon Statistical Delay Prediction under Process Variations
Confidence Scalable Post-Silicon Statistical Delay Prediction under Process Variations
复制标题
工艺变化下的置信度可扩展的硅后统计延迟预测
DOI：
10.1145/1278480.1278609
复制
发表时间：
2007
期刊：
影响因子：
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通讯作者：
S. Sapatnekar
中科院分区：
文献类型：
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作者：
Qunzeng Liu;S. Sapatnekar
由于纳米级集成电路的变异性趋势增加，统计电路分析变得至关重要。我们提出了一种新的后硅分析方法，该方法从少量片上测试结构中收集数据，并将这些信息与前硅统计时序分析相结合，以获得窄的，特定于芯片的时序pdf。实验结果表明，对于所考虑的基准集，在考虑所有参数变化的情况下，我们的方法可以得到标准差比SSTA结果平均小83.5%的PDF。该方法可扩展到较小的测试结构开销。
Due to increased variability trends in nanoscale integrated circuits, statistical circuit analysis has become essential. We present a novel method for post-silicon analysis that gathers data from a small number of on-chip test structures, and combines this information with pre-silicon statistical timing analysis to obtain narrow, die-specific, timing PDFs. Experimental results show that for the benchmark suite being considered, taking all parameter variations into consideration, our approach can get a PDF with the standard deviation 83.5% smaller on average than the SSTA result. The approach is scalable to smaller test structure overheads.