Ultralow-Power (1.59 mW/Gbps), 56-Gbps PAM4 Operation of Si Photonic Transmitter Integrating Segmented PIN Mach–Zehnder Modulator and 28-nm CMOS Driver
Ultralow-Power (1.59 mW/Gbps), 56-Gbps PAM4 Operation of Si Photonic Transmitter Integrating Segmented PIN Mach–Zehnder Modulator and 28-nm CMOS Driver
复制标题
集成分段 PIN Mach-Zehnder 调制器和 28 nm CMOS 驱动器的硅光子发射器的超低功耗 (1.59 mW/Gbps)、56 Gbps PAM4 操作
DOI:
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发表时间:
2018
影响因子:
4.7
通讯作者:
K. Morito
中科院分区:
文献类型:
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作者:
Shinsuke Tanaka;T. Simoyama;T. Aoki;Toshihiko Mori;S. Sekiguchi;Seok;Tatsuya Usuki;Yu Tanaka;K. Morito
A highly power-efficient silicon (Si) photonic PAM4 transmitter was developed by integrating a Si segmented Mach–Zehnder modulator and a CMOS driver chip. Si p-i-n-type phase shifters are directly driven with a CMOS inverter driver array to realize a low power operation. A passive <italic>RC</italic> equalizing technique was adopted to extend the modulation bandwidth up to 20 GHz while maintaining a low power consumption. By integrating a passive <italic>RC</italic> filter within the photonics chip, we achieved a very compact foot print for the transmitter (450 × 950 <italic>μ</italic>m). The fabricated modulator exhibited a low VπL of 0.19 V·cm and a moderate insertion loss of 23.7 dB/cm. The transmitter successfully demonstrated clear eye openings of PAM4 signal up to 56 Gbps together with a record-high-efficiency of 1.59 mW/Gbps. A low bit-error-rate below KP4 FEC limit ( <inline-formula><tex-math notation="LaTeX">$ <{ ext{2.0}} imes { ext{10}}^{-4}$</tex-math></inline-formula>) was also confirmed at 50-Gbps PAM4 operation even with an unequalized receiver.