Data path synthesis in digital electronics. I. Memory allocation
Data path synthesis in digital electronics. I. Memory allocation
复制标题
数字电子学中的数据路径综合。
DOI：
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复制
发表时间：
1996
影响因子：
4.4
通讯作者：
C. Chen
中科院分区：
文献类型：
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作者：
C. Chen
数据路径由存储器元件（即，寄存器）、数据运算器（即ALU）和互连单元（即总线）来控制数字系统中的数据传输。在文献中已经提出了许多方法来分配硬件的数据路径综合，但是，只有单端口存储器被认为是寄存器分配和多端口存储器综合没有有效的综合方法。提出了一种新的基于多端口存储器的数据通路综合设计方法，该方法既可以应用于硬件分配算法，也可以作为后处理器应用于已综合的数据通路，以达到更好的设计效果。应用这种方法的不同的综合实例的说明。结果和改进，在以前的技术证明。在基准测试上的实验显示了非常有希望的结果。
A data path consists of memory elements (i.e., registers), data operators (i.e. ALUs) and interconnection units (i.e. buses) to control the data transfers in the digital system. Many approaches to hardware allocation for data path synthesis have been proposed in the literature; however, only single-port memory is considered for register allocation and no efficient synthesis approach for multiport memory synthesis. A novel design methodology for data path synthesis using multiport memories is proposed which can be applied to hardware allocation algorithms or to already synthesized data path as a postprocessor to achieve a better design. Illustrations of applying this method to different synthesis examples are presented. Results and improvements over previous techniques are demonstrated. Experiments on benchmarks show very promising results.