Feasibility of monolithic and 3D-stacked DC-DC converters for microprocessors in 90nm technology generation
Feasibility of monolithic and 3D-stacked DC-DC converters for microprocessors in 90nm technology generation
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用于 90nm 技术一代微处理器的单片和 3D 堆叠 DC-DC 转换器的可行性
DOI：
10.1145/1013235.1013302
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发表时间：
2004
期刊：
影响因子：
--
通讯作者：
V. De
中科院分区：
文献类型：
--
作者：
G. Schrom;P. Hazucha;J. Hahn;V. Kursun;D. Gardner;S. Narendra;T. Karnik;V. De
微处理器输入电流的快速增加导致成本上升，去耦电容器和电源布线占用主板真实的空间。我们通过分析表明，片内开关DC-DC转换器对于未来的微处理器功率传输是可行的。DC-DC转换器可以在现有的CMOS工艺（90 nm-180 nm）中使用后端薄膜电感器模块制造。我们表明，85%的效率和10%的输出电压下降，可以实现4：1，3：1和2：1的转换比，面积开销为5%，没有额外的芯片去耦电容。4：1转换可实现3.4/spl倍/更小的输入电流和6.8/spl倍/更小的外部去耦。
Rapidly increasing input current of microprocessors resulted in rising cost and motherboard real estate occupied by decoupling capacitors and power routing. We show by analysis that an on-die switching DC-DC converter is feasible for future microprocessor power delivery. The DC-DC converter can be fabricated in an existing CMOS process (90nm-180nm) with a back-end thin-film inductor module. We show that 85% efficiency and 10% output voltage droop can be achieved for 4:1, 3:1, and 2:1 conversion ratios, area overhead of 5% and no additional on-die decoupling capacitance. A 4:1 conversion results in 3.4/spl times/ smaller input current and 6.8/spl times/ smaller external decoupling.